Staff Engineer

Role Overview

We are seeking an experienced Staff Engineer to lead ASIC SOC Verification for advanced memory technologies. You will architect comprehensive verification plans using SystemVerilog (SV) and Universal Verification Methodology (UVM), ensuring robust validation of SoC architectures, test controllers, MBIST, and functional vectors.

Key Responsibilities

• Create and develop SV/UVM-based SoC verification strategies for Test Controller, MBIST, and Functional Vector generation.
• Design high-performance monitors to measure metrics within the Verification Environment.
• Collaborate with Architecture, Design, and Tester teams to define ASIC test vectors and functional patterns.
• Automate verification environment development flows to enhance team efficiency.
• Lead Vectors Bring-up activities and support ATE/Tester teams for Functional Characterization on Silicon/Wafers.

Qualifications

• Bachelor's or Master's degree in Engineering with 7+ years of SOC/IP Verification experience using SV/UVM.
• Proficiency in AI tools and methodologies integrated into verification workflows.
• Strong knowledge of Test Controller, MBIST, and DFT architectures (PCIE, LPDDR*, ONFI/NAND).
• Expertise in scripting languages: Python, Perl, TCL for automation.
• Solid skills in problem-solving, constrained random testing, debugging, and communication.