Sr Engineer

Renesas Electronics is seeking a skilled Senior Physical Design Engineer to join our semiconductor backend team in Noida, Uttar Pradesh. This role involves contributing to the physical design cycle, including synthesis, UPF, VCLP, and LEC closure for complex System-on-Chip (SoC) designs. You will collaborate closely with Physical Design, DFT, and Front-End teams.

Key Responsibilities:

• Perform RTL synthesis from elaboration to final sign-off.
• Understand the physical design cycle and inter-team handshaking.
• Execute and debug logic equivalence checks (LEC) across various netlists.
• Develop and maintain UPF specifications, ensuring alignment with power intent.
• Conduct low power checks and analysis.
• Automate design flows using TCL scripting.

Required Qualifications:

• Minimum 5 years of experience in Physical Design for SoC.
• At least 2 years of hands-on experience in Physical Design for SoC designs.
• Exposure to synthesis processes and low-power design methodologies.
• Hands-on experience with UPF creation and power-domain modeling.
• Proficiency with tools such as Cadence Genus, Stylus, Synopsys Fusion Compiler, Conformal, and VCLP.
• Strong TCL scripting skills; Perl/Python experience is a plus.

Preferred Qualifications:

• Experience with advanced nodes (7nm / 5nm or below).
• Exposure to physical-aware synthesis.
• Understanding of UPF modeling constructs.