Soc front

About the Job

We are looking for an experienced engineer to join our team working on a high-performance networking System-on-Chip (SoC). This role requires driving SoC-level lint, CDC and RDC closure. Ensure RTL synthesis readiness and resolve synthesis issues.

Responsibilities:

• Develop and review timing constraints
• Analyze timing reports and identify RTL critical paths
• Work with RTL and backend teams on timing improvements
• Review clock/reset architecture and crossing schemes
• Manage technical waivers and front-end signoff status
• Automate checks and reports using Tcl, Python or shell scripting