Senior Staff CAD & Methodology Engi...

About The Role

We are an ambitious AI hardware startup building next-generation accelerators. To achieve aggressive Power, Performance, and Area (PPA) targets on accelerated tapeout schedules, we require a robust, highly automated, and heavily optimized physical implementation and signoff flow.

Location Options

• Bangalore: Hybrid work model (2 days office / 3 days home)
• India-wide Remote options available from anywhere in India

Role Overview

You will serve as the resident expert in Innovus and Tempus, responsible for developing, debugging, and continually accelerating our RTL-to-GDSII and timing signoff flows. You will collaborate closely with Physical Design and STA leads to eliminate bottlenecks, automate manual tasks, and push the limits of EDA capabilities at advanced process nodes.

Key Responsibilities

• Flow Architecture & Automation: Architect robust physical design and signoff flows optimized for AI accelerator architectures.
• Innovus Methodology: Drive advanced methodologies in Cadence Innovus, optimizing recipes for floorplanning, placement, CTS, routing, and power grids to maximize PPA.
• Tempus Signoff Integration: Own STA and timing signoff using Cadence Tempus. Implement Distributed Multi-Scenario Analysis (DMSA) and automated ECO flows.
• TAT Reduction: Develop Python/Tcl automation and custom utilities to drastically reduce tool runtime.
• Mentorship: Act as the final escalation point for PD and Timing teams, documenting methodologies clearly.

Required Qualifications

We are looking for a professional with 9-14 years of experience in ASIC/SOC physical design, focusing on CAD or flow automation. You must possess deep expertise with Cadence Innovus (Implementation) and Tempus (Signoff STA), along with expert-level proficiency in Tcl and Python.