Senior Engineer II

Senior Engineer II - Backend Implementation

The Microchip AES Design team is seeking an experienced and motivated Backend Implementation Engineer to perform Static Timing Analysis (STA) for larger System on Chips (SOCs). As a member of the Implementation team, you will be responsible for generating timing constraints (SDC), achieving timing closure for multiple blocks and at the top level. The ideal candidate possesses strong experience with STA tools such as Tempus or Primetime and has in-depth knowledge of timing constraints.

Job Responsibilities:

• Perform STA timing closure for multi-million hierarchical complex designs ranging from 16nm to 3nm technology nodes.
• Lead and drive team members to complete Implementation activities.
• Complete timing closure for blocks & top level in advanced process nodes.
• Develop constraints/SDC and perform pre- and post-layout timing closure. Experience with UPF/CPF is an added advantage.
• Optimize design performance through timing closure and power optimization.
• Develop and maintain design constraints and timing models.
• Analyze and debug complex timing issues.
• Analyze Physical timing challenges and provide guidance for placement & CTS (Clock Tree Synthesis).
• Ocasionally travel may be required as needed.
• Use metric-driven techniques to help ensure first-pass working silicon.
• Communicate regularly with the implementation and project team to resolve issues, and communicate status to Project Management.

Job Qualifications:

This position requires at least a B.E/B.Tech/M.Tech in Electronics with 7+ years of STA experience in a fast-paced environment. Key requirements include:

• Expertise in Implementation activities: Static Timing/Crosstalk Analysis and timing closure.
• Proficiency with STA Tools (Primetime or Tempus).
• Strong programming knowledge in Perl, TCL, Shell scripting, and/or Python.
• Excellent oral and written communications skills to collaborate effectively with teams across the globe.
• A strong understanding of timing closure and power optimization techniques.
• Must have a good working knowledge of Verilog.