Principal Silicon Engineer

Overview

The Data Processing Unit (DPU) team at Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC capable of efficiently handling large data streams. Our integrated design empowers teams with increased agility delivering significantly superior performance compared to CPU-based alternatives.

Role Summary

We are seeking Full-chip Integration professionals with solid understanding of C4/package interfaces, chip finishing, RDL (Redistribution Layer), and power delivery solutions for our DPU silicon team. You will take ownership driving fullchip integration execution from early design exploration to signoff.

Key Responsibilities

• Take ownership and responsibility for our full-chip/package integration lifecycle including final tapeout closure with vendors like TSMC 5nm process or below.
• Active role in early-phase design planning covering die size planning, floorplanning, C4/microbump development, RDL insertion & optimization.
• Develop and maintain full-chip methodologies; collaborate with vendor partners to align workflows with industry best practices addressing tool-related issues improving reliability of finishing processes.
• Define integration milestones across project phases managing interactions between package team and vendors ensuring continuity from system design through signoff.
• Manage multiple power domains & islands ensuring correctness robustness identifying resolving power delivery integrity issues providing guidance for floorplan adjustments to address continuity concerns throughout the entire board-to-chip stack.