Mulya Technologies•1h ago
LinkedIn
Principal Engineer
Greater Hyderabad Area
Full Time
Senior Level
Full Job Description
- Own the design of one or more high-speed analog/mixed-signal blocks for SerDes PHYs, from specification and architecture through schematic design, simulation, and post-layout sign-off.
- Contribute across the PHY, including transmitter (serializer, driver, DAC-based TX, FFE), receiver (CTLE, DFE, samplers, ADC-based front end), clocking (PLL/DLL, phase interpolator, duty-cycle correction, CDR or forwarded clock), and supporting circuits (termination, deskew, bias, references).
- Derive block-level specifications and budgets for jitter, noise, linearity, power, and area from link-level requirements, working closely with the architecture team.
- Verify designs across PVT corners, Monte Carlo, and extracted parasitics, including EM/IR and reliability checks.
- Guide layout engineers on floorplanning, matching, and critical routing.
- Partner with SI/package, DSP, digital, and verification teams on calibration, link training, and adaptation, and provide behavioral models for system-level simulation.
- Support silicon bring-up, lab characterization, and debug.
- Lead design reviews and mentor junior engineers.
Company
Mulya Technologies
Mulya Technologies is a stealth-mode early-stage startup focused on developing high-bandwidth, low-power interconnect solutions for next-generation compute and datacenter systems. Their work spans die...
Greater Hyderabad Area
Posted on LinkedIn