Principal ASIC Design Engineer

About the Role

Synaptics is leading the charge in AI at the Edge. We are seeking a highly experienced Principal ASIC Design Engineer to provide technical leadership across SoC architecture, design, integration, verification, implementation, and silicon bring-up.

Your Impact

• Architectural Leadership: Define and review SoC/micro-architecture, clock/reset systems, interfaces, and integration requirements with cross-functional teams to balance PPA (Power, Performance, Area) and cost.
• Poer Optimization: Drive power analysis across architecture, RTL, and physical implementation using UPF methodologies for multi-power-domain SoCs.
• RTL & Integration Quality: Lead RTL design coding quality, Lint, CDC/RDC/SDC closure, and ensure IP deliverables meet program milestones with the Verification team.
• Cross-Functional Convergence: Partner on floorplanning, synthesis, STA, timing closure, congestion, power integrity, and PPA optimization to solve complex front-end/back-end issues.

Key Competencies

You will bring expert knowledge of ASIC/SoC design methodologies, low-power designs (UPF), strong RTL coding skills (Verilog/SystemVerilog/VHDL), clock/reset architecture, synthesis/STA/DFT tools, and Perl/Python/Tcl scripting for efficiency.

• Strong understanding of EDA flows from Synopsys, Cadence, or Siemens.
• Analytical mindset to balance tradeoffs in complex systems.
• Excellent communication skills to mentor engineers and influence technical direction across global teams.