Physical Design Engineer

Overview

We are seeking an experienced Physical Design Engineer with 1 to 2 years of hands-on expertise in block-level or sub-chip physical implementation. In this role, you will collaborate closely with senior technical leads and cross-functional teams including synthesis, static timing analysis (STA), and physical verification units.

Key Responsibilities

• Floorplanning & Power Planning: Lead block-level floorplanning activities, manage pin assignments, place macros efficiently, and design robust low-IR drop power delivery networks (PDNs).
• Placement & CTS: Execute netlist placement strategies, optimize logic structures for performance, and perform Clock Tree Synthesis (CTS) to meet strict skew and latency targets.
• Routing & Optimization: Manage detailed global/track routing processes, resolve congestion hotspots and crosstalk noise issues while optimizing Power, Performance, and Area (PPA).
• Static Timing Analysis (STA): Conduct comprehensive STA using industry-standard tools like PrimeTime or Tempus. Trace setup and hold violation paths to implement effective ECO fixes across multi-mode multi-corner (MMMC) conditions.
• Physical Verification: Debug and resolve Design Rule Checks (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), and Antenna effect checks to ensure clean, compliant physical layouts ready for tape-out.
• Power Analysis: Partner with senior engineers on EM/IR drop analysis covering both static and dynamic scenarios, implementing targeted power-aware fixes.
• Automation: Develop and maintain scripts in Tcl, Python, or Shell to automate design flow execution and custom data parsing within Linux environments.