Physical Design Engineer

Join Qualcomm as a Physical Design Engineer and play a pivotal role in the implementation of Place and Route (PNR) for Qualcomm's System-on-Chips (SoCs). You will be responsible for the end-to-end PNR implementation, encompassing floorplanning, placement, clock tree synthesis (CTS), and post-route optimization for cutting-edge technologies. This role requires hands-on experience with PNR flows and a strong understanding of optimization techniques. A mandatory requirement is sign-off knowledge, including Static Timing Analysis (STA), power analysis, formal verification (FV), low power verification, and physical verification (PV). You will work on the latest technology nodes, such as 4nm/5nm/7nm/10nm, and will be expected to possess good knowledge of Unix/Linux environments, with proficiency in Perl/TCL scripting fundamentals. We are looking for quick learners with strong analytical and problem-solving skills who can take complete ownership of PNR implementation tasks. A minimum of 2 years of hardware engineering experience or related work experience, along with 2+ years of experience with PNR flows in advanced tech nodes, is required.