Physical Design Engineer

Qualcomm is seeking a Physical Design Engineer to join our team, focusing on Place and Route (PNR) implementation for our cutting-edge System-on-Chips (SoCs).

General Summary

This role involves hands-on PNR implementation for Qualcomm SoCs.

Key Responsibilities

• Extensive experience with Floorplanning, PNR, and Static Timing Analysis (STA) flows.
• Strong knowledge of Placement, Clock Tree Synthesis (CTS), and optimization techniques.
• Solid understanding of signoff domains, including Logic Equivalence Checking (LEC), Clock Leakage Power (CLP), and Power Distribution Network (PDN) analysis.
• Proficiency in Unix/Linux environments with Perl/TCL scripting fundamentals.
• Full ownership of PNR implementation, including Floorplanning, Placement, CTS, and post-route analysis on the latest technology nodes.
• Mandatory signoff knowledge encompassing STA, power analysis, formal verification (FV), low power verification, and physical verification (PV).
• Demonstrated ability to be a quick learner with strong analytical and problem-solving skills.

Qualifications

• Minimum of 1 year of experience in Hardware Engineering or a related field.
• Minimum of 1 year of experience with PNR flow on advanced technology nodes (e.g., 4nm, 5nm, 7nm, 10nm).