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Front-End Silicon Design & Integration (FEINT) Engineer - Security IP (SECIP)

Join AMD's Security IP (SECIP) team as a Front-End Silicon Design and Integration (FEINT) Engineer. This role involves the design and verification of embedded micro-processor subsystems and hardware accelerators critical for enhancing system performance and functionality. These Intellectual Property (IP) blocks deliver high-performance functions for System on Chip (SoC) products across AMD's client computing, server, discrete graphics, and gaming business units.

As a FEINT Engineer, you will be responsible for RTL synthesis and Performance, Power, and Area (PPA) analysis to optimize RTL design quality of results (QoR). You will also develop, adopt, and automate RTL static design rule checks, perform Electronic Change Order (ECO) and Logic Equivalence Checking (LEC) operations, and support SoC integration of IPs.

Ideal Candidate Profile:

We are seeking a talented FEINT engineer with a strong track record of technical ownership and execution. You should be a forward-thinking individual capable of optimizing workflows, anticipating and resolving technical challenges, and thriving in a competitive environment while mentoring team members. Excellent written and verbal communication, problem-solving skills, attention to detail, and professional interpersonal capabilities are essential.

Key Responsibilities:

• Develop RTL synthesis strategies and scripts for synthesis, timing path analysis, and PPA analysis at subsystem and block levels to improve RTL design QoR.
• Formulate ECO strategies, execute netlist and/or conformal-assisted RTL ECOs, perform LEC on resulting netlists, and resolve discrepancies.
• Develop, adopt, and automate RTL static design rule checks in collaboration with Back-End Integration and Physical Design teams. Triage and debug design rule violations with the RTL Design team and support IP integration with the SoC team.
• Develop and adopt FEINT design and verification infrastructure, methodologies, and tools.

Preferred Experience:

• Minimum 2 years of relevant experience for BSc, or 1 year for MSc.
• Proven understanding of RTL design, synthesis, and ECO principles.
• Excellent knowledge of FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, etc.
• Proficiency in Verilog, C/C++, and scripting languages (Tcl, Ruby, Perl, Python, Makefile).
• Strong skills in the Unix/Linux environment.
• Familiarity with RTL coding techniques for competitive PPA-measured QoR.
• Familiarity with RTL coding style for clean design rule checks (LINT, CDC, etc.).
• Good understanding of gate-level circuit design and physical design concepts/methodologies.
• Familiarity with VCS/Verdi and SPG-based (dynamic/static) verification environments.
• Excellent communication skills (written and oral).
• Self-motivated and committed to achievement.

Academic Credentials:

• Bachelors or Masters Degree in Electrical Engineering, Computer Engineering, or a related field.
• Masters Degree preferred.

This posting is for an existing vacancy.