Front End Design Engineer

About Qualcomm India Private Limited

Qualcomm India Private Limited is a leading semiconductor organization in India, focused on the design and development of high-end chips utilizing advanced technologies. The company's growing needs are supported by a robust Custom/Semi-Custom Implementation (CSI) team dedicated to high-speed and low-power Intellectual Property (IP) development for System-on-Chip (SoC) applications. This role involves significant contribution to RTL-GDS implementation, driving innovation in close collaboration with other design teams.

Job Summary

The CSI team is seeking an experienced engineer to work on RTL-GDS HM implementations using custom flows and methodologies for CSI IPs. This position requires innovation and collaboration within the design teams.

Minimum Qualifications

A Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, combined with 3+ years of experience in Hardware Engineering or a related role.

Alternatively, a Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 2+ years of relevant experience.

A PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 1+ year of relevant experience will also be considered.

For candidates within Qualcomm CSI, 4+ years of experience is required.

Job Responsibilities

• Design and development of custom macros, including schematic design at the block level (e.g., RegArray, memory subsystem).
• Conduct frontend verification and model generation.
• Perform CLP/PAGLS/LEC verifications at the block level.
• Execute functional verification using spice/gatesim.
• Achieve timing signoff using PT.
• Collaborate effectively with various cross-functional teams.

Skillset and Experience

• 2-4 years of experience is required.
• Proficiency in transistor circuit design and block-level logic design for memory subsystems and data paths.
• Expertise in Static Timing Analysis (STA) for design closure, including Set-up, Hold, MPW, and Transition requirements.
• Experience in design verification using ESPCV & LEC, and simulation using Finesim & HSPICE.
• Proficiency in front-end RTL design, including Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler, LEC, PLDRC, Static Timing Analysis, and PTPX.
• Experience with physical design using industry-standard RTL2GDS flow, including Synopsys ICC2 and Cadence Encounter.
• Scripting skills in Perl/Python/Shell/Tcl for productivity enhancements are a plus.
• Experience in IP development, encompassing custom macro transistor-level design, physical integration, collateral generation, and flow development, with a focus on PPA quantification.
• Ability to interface with Process Technology teams to understand advanced technology node requirements (DRC, DFM).
• Experience working with cross-functional teams (Architecture, Test/Verification, Product, CAD, Layout, Physical Design) to define and implement specifications.
• Proficiency in transistor-level implementation of blocks using CMOS, Domino, Cell-Based, and Data Path styles.
• Implementation of power/clock gating techniques and industry-standard as well as custom Design for Testability (DFT) techniques.
• Expertise in clock distribution using custom/CTS techniques for low skew/latency/power.
• Skill in implementing block layouts using custom/compiler techniques with custom/semi-custom/stdcell libraries.
• Experience with block-level floor planning using custom and/or tiling techniques.