Engineer

Role Overview
Join the PHYSICAL IP – MEMORY group as a Memory Layout Designer at Arm's Noida facility. You will work on innovative memory architectures in cutting-edge technology nodes to deliver best-in-class Arm systems.

Key Responsibilities:

• Create full-custom layouts for high-performance arrays and memory blocks from planning stages through final verification.
• Interpret and implement physical design rules across advanced manufacturing processes.
• Perform custom layout and verification of complex memory cells, including floor planning, metal planning, and efficient layout techniques to optimize PPA (Power, Performance, Area).
• Serve as a DRC/LVS/DFM resource for circuit and test layouts using Calibre tools.
• Conduct electro-migration and IR checks to ensure reliability and integrity.

Requirements:

• Bachelor's or Master's degree with 2+ years of layout design experience.
• Proficiency in Cadence Virtuoso layout systems.
• Ability to manage complex, hierarchically structured circuits schematics.
• Skill in optimizing power, speed, and area for data paths, bitcell arrays, word line drivers, and control blocks.