DFT Architect

About the Company & Role:

EnCharge AI (enchargeai.com) is a leader in advanced AI hardware and software systems for edge-to-cloud computing. Their next-generation in-memory computing technology offers orders-of-magnitude higher compute efficiency, enabling massive potential for power- and space-constrained applications.

Role: DFT Architect (14-18 years experience)

About the Job

Developing silicon for Edge Computing requires balancing high-performance data processing with extreme power efficiency. As the Design for Test (DFT) Architect, you will architect our testing strategy to ensure data center chips are flawlessly manufacturable and resilient for edge deployment.

Key Responsibilities

• Architectural Leadership: Define end-to-end DFT architecture for complex SoCs (Hierarchical DFT, Scan compression, MBIST).
• Edge-Specific Reliability: Develop strategies for In-System Test (IST) and POST to ensure chip health in remote environments.
• Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Logic BIST.
• Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to maximize coverage while minimizing area/power overhead.
• Post-Silicon Validation: Lead ATE bring-up/debug phases to root-cause failures and optimize test time.

Technical Requirements

• Experience: 14-18 years in DFT with at least 2 years in a leadership role.
• Tools: Mastery of Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus.
• Memory & Logic Test: Deep expertise in MBIST with repair and IEEE 1149.1/6 boundary scan.
• Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm or below).
• Low Power: Experience managing DFT in multi-voltage/power-gated designs for edge efficiency.